A senior Google executive has reportedly confirmed that the firm has found a workaround to the AI-led memory chip supply crunch and price hikes that have stalled the entire tech sector: recyc
A senior Google executive has reportedly confirmed that the firm has found a workaround to the AI-led memory chip supply crunch and price hikes that have stalled the entire tech sector: recycling DDR4 memory from retired servers and using it in its newest AI machines.
Senior director of supply chain infrastructure, Nikhil Cherian, said that even with the DDR4 recycling pivot, the tech giant is still struggling to find enough chips for its AI systems. The only lasting solution to the extremely tight supply situation, as Cherian put it, is for memory makers to build more capacity and fast.
Google is not alone in seeking solutions to avoid AI accelerators that cost billions of dollars to build and sit idle while they haggle over per-module pricing for memory bandwidth that is hard to come by.
Meta laid out its own method of recycling DDR4 behind Compute Express Link, or CXL, a standard that pools older DDR4 and newer DDR5 in a machine, in a paper it published earlier this year.
Marvell’s associate vice president of product marketing, Khurram Malik, told EE Times that hyperscalers are finding ways to prolong the shelf life of DDR4 modules using the CXL controllers instead of them going obsolete when servers migrate to DDR5-only platforms.
Meta said it counted as much as a 25% efficiency in server count on some inference workloads across millions of servers. Even average latency dropped about 29% on distributed cache systems.
However, the workaround did not work for every memory chip. Meta said off-the-shelf CXL products bundled controllers with DRAM, which blocked reuse of existing DDR4 stockpiles. Those stacks also caused expansion memory to run roughly ten times slower on bandwidth and about 60% higher on latency than directly attached DRAM.
Meta’s answer to that problem was its in-house Vistara ASIC. That specific model is built to be reused, with power efficiency and low latency advantages already built in. On top of all that, the firm also pairs the ASIC with software that monitors workload and switches it off where unacceptable delay is detected.
Memory chip prices continue to go up, with the arc getting steeper as the AI buildout continues to soak up everything manufacturers can put out. Counterpoint Research reported an 80% to 90% quarter-over-quarter price hike in Q1 of 2026.
Marvell’s estimation came in at 90% to 95% single-quarter increments on the price of conventional DRAM, with hyperscalers expected to spend roughly 30% on memory in 2026, up from about 8% in 2023 and 2024.
TrendForce expects another 13% to 18% quarterly rise in conventional DRAM contract prices in the third quarter of 2026.
Supply is not catching up soon. As Cryptopolitan reported, China’s ChangXin Memory Technologies has hit a capacity ceiling near 240,000 wafers a month, held back by US export controls and yields Counterpoint estimates run 42% below Samsung and SK Hynix. SK Hynix has committed about $38 billion to two new fabs, but its Y2 DRAM plant is not expected to reach the cleanroom stage until mid-2029.
The pressure could get worse before more silicon arrives. Two unions representing about 10,000 Micron workers in Taiwan are weighing a strike vote in September over how bonuses are calculated, Cryptopolitan reported, and Micron is one of three firms that control roughly 94% of the DRAM market. A stoppage at its Taiwan fabs, which cannot be relocated quickly, would tighten a market SK Hynix chief Kwak Noh-Jung expects to stay short until the end of 2030.
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